In addition clock plans to IBIS-digital station must be able to read digital clock and much more wi

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Article clock plans on hourly panel here I am at the end of station clock prototype performed digitally (digital clock situated directly at the station and showing accelerated time model). Benefits of station digitally in particular, in that the operator station and Firovo you do not prevaricate clock plans neck to see the big clock on the wall or somewhere in the middle of the room BigBen. And especially for younger children is more appropriate than the usual digital information Needle analog clock without numbers, but we also zošiťáky with numbers ... send digital data record is more reliable to analog pulse in the fact that if the clocks change clock plans snap any time, additional information about the new time Hours remedy to correct. Hours, however, I do not just digital data IBIS (European data bus for public transport) used in BA Rail, but also for conventional analog system -12/24V +, which is much more prevalent in meetings than any digital clock plans solutions, not only in our country.
Reading clock plans the digital information is easy, as there is no need to ask for information or to confirm it. IBIS protocol we use in particular BA meetings, used to set the time instruction uHHMM <CR> P-hour broadcast control panel to change clock plans where HHMM is the time CR is 0x0D and P is the parity control. Hours constantly read bus and soon receive instructions u0620 <CR> example, so it is clear to them that it is necessary clock plans to set the time to 06:20. Nothing after the bus or walked.
In addition clock plans to IBIS-digital station must be able to read digital clock and much more widespread analog signal that looks the most frequent obojpolaritný rectangle (pictured far left), or less frequently as a stepped rectangle medziúrovňou zero (figure in the middle). Polarity must substitute (ie if we want to maintain the same functionality as the functioning of large analogues clock plans anchor between electromagnets) and repeated pulses of only one polarity clock do not move. Far right is the alternative, if the signal is generated, for example, a capacitor discharge. Voltage pulse reaches typically 24V or roughly half the value (12 to 15V), and more rarely (48V).
On the left is the signal processing simple, there just crop the negative half-wave and the processor to read positive and zero. In the middle (and right) is already not so, because the change from positive clock plans to zero or negative zero does not change anything. Hours must interject to change the level from zero to a positive value and the decrease from zero to negative. Here is a solution núkajúce evaluating the absolute value of the middle and right signals are unreliable for the left signal, because the steep rectangle is zero extremely clock plans short and may not be recognized. Furthermore, it is still to be seen alternating sequence of positive and negative pulses, in order to maintain consistent feature of these hours with classical analog.
Time display would be visible to Radio Clock from the other end of the long station, but they should not be bulky and cumbersome. A clock that is legible even in low light, some are better than LED, LCD displays, even backlit. In analogue mode, you need to know to set the clock manually. Power ideally those that already use the meeting.
I considered clock plans the moment the clock to equip the compatibility Loconet, as well as the instructions for a clock. Preferably Loconetových hours compared to traditional analog or digital solutions is any particular savings cabling because LocoNet is always available directly at the station. The disadvantage, however, is that the distribution LocoNet time in our country practically not used at all, moreover, probably caused by the fact that the transmission time is not a function of each central. With more than three wise it is further burdening undesirable, although time communication is actually negligible compared to the main, ongoing between Fred and headquarters. And yet another disadvantage specific voltage levels for logic level Loconet. Do I Loconet So, in these hours ever ventured. Engagement
It is essential ATMEL ATMEGA clock plans 2313 processor, which multiplexed light on display, reads status clock plans of buttons and inputs of course. Entry is reliable because recognizing these types of pulses evaluated dual comparator and checks if the input voltage higher than about 5.3V, 0.3V below the negative or somewhere in between.
Choosing the type of comparator proved important as I compare the input to the power supply. Ideal for this purpose is MCP6542 that works correctly in the two extreme values. For example, under the ICL7621 datasheet bear input 0.3V power off both ways as well, but it worked well only at voltages below the negative clock plans voltage